This is a case study of a successful partnership between AMD and Mentor Graphics Consulting Division (MCD) to create a DRC ruledeck for a new IC technology. This technology is a 0.18m CMOS multiple-well STI Flash memory technology, which includes over 20 different transistor and component types. The major phases of the project were: existing ruledeck audit; DRC code creation and testing; and physical QA test suite creation. The technology, lead product, and verification decks were developed concurrently. The ruledeck had to be completed on a tight timeline (8 weeks), and was further challenged by design-rule revisions late in the design cycle.

Key success factors were: careful and complete definition of scope of work; effective use of AMD and MCD expertise; modular code development; disciplined project tracking; and co-development of a QA layout test suite. AMD Design, CAD, and technology engineers partnered with MCD consultants to write efficient code and to eliminate false DRC error flags. MCD was able to code several rules which had not previously been attempted by AMD, due to the complexity of the checks required.

MCD then supported tapeout of AMD’s lead product, by implementing multiprocessor “Turbo” Calibre, (HLVS, HDRC) on our compute farm. This dramatically reduced our full chip LVS run times, from 4 hours to under 40 minutes.

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