Parasitic Effects, Nanometer Silicon Modeling and Calibre xRC
With 90 nm designs in production, 65nm in view, and copper technology commonplace, serious challenges are confronting designers that have profound impact upon the success of today’s sophisticated analog mixed-signal (AMS) designs. These challenges stem from a combination of factors that emerge in nanometer scale design, such as shrinking feature sizes, finer line widths, longer interconnect, more routing layers, and more analog content. Signal integrity must be maintained and timing closure achieved even as complexity rises and functional execution is accelerated. Transistor-level modeling accuracy, previously required only in analog is now required across the entire design flow.
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