Packet Subsystem On A Chip
As the world gets connected, more and more systems rely on access to the network as a standard part of product configuration. Traditional circuit-based communications systems like the telephone infrastructure are gradually moving towards packet-based technology.
Even technologies like Asynchronous Transfer Mode (ATM) are starting to yield to the Internet Protocol (IP) in places. All of this has dramatically increased the need forpacket-processing technology.
The content being passed over this infrastructure has increased the demands on available bandwidth. Core routers target 10 Gbps; edge and access equipment work in the 1-5 Gbps range. Even some end-user equipment is starting to break the 100 Mbps range. The question is how to design systems to accommodate these speeds.
These systems implement a wide variety of network protocols. Because the protocols start out as software, it’s easiest for network designers if as much of the functionality as possible can remain in software. So the further software programmability can be pushed up the speed range, the better. Although FPGAs can handle network speeds as high as 10 Gbps, RTL has typically been required for 1 Gbps and higher.
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