Stimulus generation requirements are expanding. A variety of factors are driving the complexity of verification stimulus, including higher levels of intellectual property integration in designs, increased levels of software interaction in hardware functionality, more complex bus protocols, and the need to reuse significant portions of verification environments. This imposes new requirements in stimulus generation, including the ability to:

  • Create stimulus modules that run in a controlled fashion, in serial or parallel.
  • Separate the stimulus generation from the actual testbench.
  • Layer stimulus in the generation of a single protocol and encapsulate layered stimulus into a single protocol. One example of this is Ethernet over SONET.
  • Package stimulus generation with a verification IP component.

These requirements are met in OVM with the sequences facility. Sequences allow a verification engineer to construct complex stimulus operations using a building-block approach. Sequences may be written, shared, and reused to generate the desired stimulus with less effort and greater modularity than more traditional testwriting approaches.

This document provides an overview of sequences and shows all the code necessary to use sequences within the OVM.

Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.