The present trend in integrating multi processing cores in a single die demands an efficient on-chip communication infrastructure design. Though the Packet-Switched Network on Chip with electronic routers provide good solution in terms of throughput and latency, the increasing trend in CMPs may pose problems with respect to On-chip temperature and power consumption. Clearly, reducing the power dissipated by the NoC allows more of the limited power budget to be devoted to the cores, which directly improves the overall system’s performance per-watt. To solve these critical issues and to improve the over-all performance of the future NoCs, we should focus on finding the alternatives to the metal/dielectric communication structure.