Overcoming Physical Verification Challenges In a 100-million Transistor SoC Design
This paper chronicles how Fast-Chip, Inc., a fabless semiconductor company that designs high-performance communications integrated chips, and Mentor Graphics, an industry leader in EDA tools and solutions, overcame the significant physical verification (PV) challenges of a complex and sophisticated system-on-chip (SoC) integrated circuit design. It is a story of complementary architectures converging from separate points on the EDA spectrum to integrate reciprocal strengths, delivering a major innovation in network services processing.
Fast-Chip recently developed the breakthrough PolicyEdge Services Processor, a 100 – million+ transistor IC capable of operating at an aggregate rate of 10 Gigabits per second across single or multiple ports, classifying, editing and maintaining statistics on 32 million packets per second (min packet size of 40 bytes). The Policy Edge processor is the industry’s first 10 Gigabit capable application-specific standard part (ASSP) processor.
The sophistication of the PolicyEdge SoC design resulted in a formidable physical verification challenge for manufacturability, which was particularly critical, as a “first to silicon” market leadership position hung in the balance. Mentor Graphic’s industry-leading Calibre physical verification tool was the solution to the problem.
Leveraging complementary strengths, Fast-Chip’s PolicyEdge processor and Mentor Graphic’s Calibre physical verification tool were a perfect fit. Calibre’s performance on the PolicyEdge project, which helped bring a packet processing innovation swiftly into commercial reality, proved its dominance as the physical verification tool of choice for SoC designs.
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