Optimizing Xilinx FPGAs for Power
As IC processes have advanced over the last half dozen years from the 130-nanometer to the 90-nm and now the 65-nm node, at each step power management has grown in importance. It was at the 130-nm node that manufacturers started noticing that transistors leaked power, even in standby mode. At 90 nm, the operating voltage of ICs decreased, but leakage continued to rise, wasting a greater percentage of the device’s power. At 65 nm, both these trends continue. Indeed, leakage at the 65-nm node is so pronounced that many designers consider managing power as important as meeting performance specifications.
Because FPGA vendors traditionally design for a broad range of applications and endow their devices with a plethora of high-speed transistors, FPGAs have not been the most power-conservative devices. Like other silicon designed in the most advanced processes, they use transistors that leak. However, designers can leverage an FPGA’s programmability and use related tools to accurately estimate power and then employ optimization techniques to make their FPGA designs and the PCBs that contain them much more power efficient.
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