This white paper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping, Clock frequency, and Quality of Service (QoS), configuration of a generic DDR memory controller for a given set of use cases and performance requirements. After a brief overview of the use case and platform, we first cover the necessary preparation work: the assembly of the SoC platform model and the creation of the trace-based traffic profile. Then we discuss the step-by-step optimization of the memory subsystem, such that the specific throughput and latency requirements of each component are satisfied.