Within the past several years, integrated circuit (IC) design and manufacturing technology nodes have progressed rapidly from 0.13um to 65nm and 45nm. Whatever the technology node, the goal is the same: that both designer and manufacturer focus most of their effort into making the chip yield as high as possible. Much evidence has shown that the final yield is closely linked to the pattern transfer from design to wafer. With critical dimension shrinks, a considerable challenge is maintaining high fidelity while transferring the patterns.

Since the process window is now very limited, a tiny process deviation may cause large critical dimension variation, which can result in significant device character change. Micro-lithography combined with Optical proximity Correction (OPC) is supposed to be the most critical stage in pattern transfer stage, but conventional OPC always uses a nominal model that will not take random process variation into account during the application of OPC. This paper presents an experiment in OPC involving the process window model that demonstrates substantial improvement in pattern fidelity.

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