Compiler optimization technology makes a critical contribution to fully exploiting the performance potential of RISC processors. Because RISC processor performance is more sensitive to delays caused by fetching instructions and data from memory, it is important that the compiler minimizes LOAD/STORE operations and makes optimal use of the instruction pipeline.

In this paper, we introduced several optimization techniques, such as aliaz analysis and interprocedural analysis that help reduce LOAD/STORE operations by giving the compiler a more comprehensive view of which variable locations are affected by the part of the program being optimized. This enhanced information allows much more aggressive optimizations to take place. We also discussed instructions scheduling, which allows the pipeline to work more effectively.

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