On the Handling of Asynchronous Events on VLIW-like DSPs
Architectures of highest-performance DSPs and multimedia processors exhibit a trend towards very long instruction words (VLIW). Their key characteristics are high on-chip parallelism in conjunction with deep execution pipelines. Exploiting the high degree of parallelism is difficult and requires sophisticated optimization tools. In contrast to general-purpose processors this optimization is done at compile-time. This has the advantage of fully deterministic behavior. However, static optimization at compile time is a conceptual contradiction to real-time processing of events. External events in DSP systems usually occur asynchronously to program execution and hence cannot be taken into account by a compile-time optimizer. This paper introduces methods and a tool to “softly” synchronize the handling of asynchronous events with a user adjustable trade-off between raw performance and determinism at the example of the 320C62xx family.
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