OMAP35xx Applications Processor MPU Subsystem: Technical Reference Manual
This paper describes the microprocessor unit (MPU) subsystem of the Texas Instruments OMAP35xx Applications Processor, which handles transactions between the ARM core, the L3 interconnect, and the interrupt controller (INTC). The MPU subsystem is a hard macro that integrates the ARM subchip with additional logic for protocol conversion, emulation, interrupt handling, and debug enhancements.
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