Off to the Races with Your Accelerated SystemVerilog Testbench
This document describes a methodology for writing SystemVerilog and OVM or UVM testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration using Mentor’s Veloce TBX solution. The methodology presented herein promotes the co-emulation (also known as co-modeling) approach and aims to maximize reuse between pure simulation-based verification and hardware-assisted acceleration.
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