Today’s equivalence checking tools cope with the complexity of today’s designs in one of two ways. One method is to decompose the design into multiple blocks and verify each block sequentially. The other method is to tune the equivalence checking tool for optimum memory utilization, so that the entire design can be verified at once. This paper examines the advantages and disadvantages of both methods and shows how Mentor’s FormalPro equivalence checker enables the best possible use of these methods to reduce debug time.

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