Novel Method for Optimizing Lithography Exposure Conditions Using Full-Chip Post-OPC Simulation
At 65 nm and below, full-chip verification of Optimal Proximity Correction (OPC) is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters. The traditional approach to this has involved selecting representative feature test patterns, placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest.
This paper reports on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that this new method results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.
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