A Novel Approach to Catch Boundary Optimization Using Logic Equivalence Checking
Boundary optimization is a technique used while logic synthesis for proper area, timing and power optimization. Boundary optimization may result in about 5-10% of standard cell area reduction and 2-5% of timing improvement. While synthesizing a design, a synthesis engineer has to decide the list modules which should be boundary optimized and which should not. Wrong boundary optimization may require setup changes for already up tool environment or sometimes re-synthesis with proper boundary optimization constraints. The proposed flow netlist corruption can be caught much before in design flow and SoC design cycle time can be reduced by ensuring of proper netlist quality.
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