New Degrees of Parallelism in Complex SOCs
New more feature-rich electronic devices appear everyday, while existing devices continue to evolve and converge into more elaborate ones. There remains, however, a strong impetus to integrate these functions onto as few silicon chips as possible, which is driving SOC complexity up at a staggering rate. Moore’s Law provides the ammunition to meet this challenge, but bringing the power of semiconductor technology to bear on SOC performance in the future will require different architectural approaches than those used in the past. The traditional techniques of pipelining and superscalar instruction issue are approaching their limits and other techniques like vector processing, multithreading, and chip multiprocessing will be called on to carry the ball.
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