As the semiconductor industry strives to keep Moore’s Law moving forward, companies are continually confronted with new and mounting challenges. The use of fin field-effect transistors (finFETs) and the recent introduction of gate-all-around (GAA) finFETs present questions of performance, scalability, and variation resilience that have yet to be fully resolved. The need for multipatterning, which has been in place since the 22 nm node, is not going away, even with the introduction of extreme ultraviolet (EUV) lithography. Complex fill requirements have emerged as a critical success factor in both manufacturability and performance in leading-edge nodes.

These factors, among others, have created significant impacts across the EDA design-to-tapeout ecosystem, particularly in physical verification. Replacing inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality helps maintain, and even grow, both the bottom line and product quality in the face of increasing technological complexity.