Never Design Another FIFO
In digital designs, first-in first-out memory queues (FIFOs) are ubiquitous constructs required for data manipulation and buffering—tasks that are often very challenging. Are all clock domain crossings properly timed and synchronized? How do I convert my 16-bit data path to 64 bits? These elements of a FIFO design are difficult and time-consuming to implement, and are often error-prone. The Xilinx® FIFO Generator core solves these challenges and provides an assortment of complex FIFO designs through a convenient, configurable graphical user interface (GUI), enabling you to focus on your system requirements.
From application notes and reference designs to IP cores, Xilinx has a long history of developing FIFOs. With the introduction of the FIFO Generator, almost any imaginable FIFO configuration is provided as a fully optimized, pre-engineered solution delivered through Xilinx CORE Generator™ software. The FIFO Generator supports a suite of memory types, including block RAM, distributed RAM, shift registers, and the Virtex™-4 built-in FIFO. The core also supports write and read interfaces with either a single common clock or dual independent clocks. These and other options are easily customizable through the GUI. In this article, we’ll highlight the benefits of the FIFO Generator solution and how it can help you quickly develop a FIFO that exactly meets your needs.
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