In early 2017, an efficient, scalable, data center-ready emulation platform gave users what they needed to address a significant evolution in SoC verification — an evolution where the complexity of SoC design demanded both comprehensive verification, as well as system-level validation early in the design cycle, often before stable register-transfer level (RTL) code was available.

Today, a new product extends the scalability of that platform while protecting customer investment in existing hardware and verification
setup. In this paper, learn about this next step that delivers an advanced verification board capable of boosting capacity as design sizes continue to grow, especially where AI/ML, GPU/CPU and networking sectors intersect each other.