My RTL is an Alien
With over 70% of today’s ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files. This paper focuses on how to create an automated process that converts ASIC design source files into a working FPGA. The techniques described will allow you to maintain one “golden” set of files that will work in both your ASIC and FPGA design environment so that, with each new revision of your ASIC design, you will be able to quickly create a revised FPGA-based prototype.
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