Multiple Workstation Equivalence Checking Provides Capacity and Performance for Regression Testing of Multimillion Gate Designs
As ten, twenty, thirty million gate designs and larger become increasingly commonplace, traditional verification In the wake of 90-nanometer and smaller geometries, this only becomes more severe. The designs that these technologies enable will include chips exceeding 70 million gates. And it wont be long before 200 million gate designs are ubiquitous. These designs will also contain individual blocks that are larger than the largest full chips many companies design today.
With increased design size and complexity, the number of design transformations that occur between register-transfer level (RTL) synthesis and final sign-off are so numerous that engineers will be compelled to utilize regression testing techniques so they can verify their designs more often, ideally with every modification. Current equivalence checking tools, which have become invaluable additions to the verification toolbox, generally lack the capacity and performance to handle thorough regression testing. However, these tools are critical and must be enhanced to analyze, verify, and debug these complex, multimillion-gate ASICs in their entirety.
This paper examines why the challenges of large, complex designs have made equivalence checking a useful tool, and it discusses why the even bigger and more complex designs on the horizon will make equivalence checking indispensable in terms of design quality and competitive advantage. We will introduce the concept of verification distance to help explain this need. And we will discuss the performance and capacity advantages of a new, scalable equivalence checking technology introduced by Mentor Graphics.
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