The number of clock domains on System-On-Chip (SoC) is demanding enhanced performance and power, and for supporting the interfaces working at different frequencies. The synchronizer logic is used to synchronize the signal traversing from one clock domain to another clock domain. Verification of such designs also imposes challenges. In the simulation-based functional verification, checkers are implemented in the testbench to verify if the performance of Design Under Test (DUT) complies with the design specification. This paper presents the challenges of implementing a semi-cycle accurate reference checking mechanism in the simulation based verification, and proposes a solution to overcome it.