Libraries provide the foundation for digital design implementation. Consequently, any inaccuracy in library creation will permeate throughout the design flow for every chip that uses that library.

As semiconductor process geometries get smaller, electrical complexity increases, making it harder to accurately model the timing, power, and signal-integrity characteristics of each standard cell. In addition to creating more complex models, characterization tools must now be tuned to match silicon more closely. In particular, non-linear waveform effects must be modeled.

This paper discusses the need for more advanced library characterization—and library characterization tools—for nanometer designs. This paper outlines best practices for library characterization, and provides examples of the impact of characterization technique on delay-calculation accuracy. These techniques are supported by most characterization systems, including Cadence SignalStorm LC.