When it is not possible to meet design objectives using a top-down flow, or your design environment dictates that you design block by block, a bottom-up modular FPGA design methodology can be used to minimize the effort to update and improve the design. By using a combination of bottom-up design style in Precision RTL Synthesis and the Block Modular Design method in ispLEVER, designers can enjoy benefits like improved quality of results, runtime, timing, area utilization and faster incremental change to large FPGA designs.

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