Modeling Total Cost of Ownership for Semiconductor IP
The design productivity gap has been widely discussed for a decade. Intel processors and other leading edge designs, like graphic processors from NVidia and ATI, achieve optimal use of available technology. But, the typical ASSP and ASIC designs are not taking advantage of CMOS technology, and are not achieving optimum unit cost per function. As a result of this problem of lagging design productivity, the ITRS identified the need to create roadmaps to improve the industry’s design productivity. This white paper discusses those roadmaps.
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