Modeling Parasitics in Sub-Micron IC Designs: Extract Them Before They Cost You a Re-Spin
This paper explains why designers must devote more attention to such parasitic effects as capacitance and resistance as process size shrinks. It describes the shortcomings of current approaches to dealing with these effects. Finally, it introduces the characteristics of today’s parasitic extraction tools, which enable designers to model parasitic effects and address them while still in the layout phase.
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