Accurate modeling of post-ECD (electrochemical deposition) surface topography variation is crucial for correct chemical mechanical planarization/polishing (CMP) simulation. Siemens and the American University of Armenia collaborated to investigate and evaluate the use of machine learning (ML) modeling techniques to predict these complicated topography variations. Using various ML methods to model post-ECD surface profiles and comparing the results enabled them to determine which architectures and models provided the best combination of running time and accuracy.


CMP is a crucial technology used during the manufacturing of multi-level interconnections of semiconductor chips and electronic devices1,2. Many process steps used in chip manufacturing require planar (smooth) surfaces on the wafer to ensure correct pattern printing during the lithography that generates structures for the next layer. CMP is the key process used to achieve the surface planarity required for accurate depth of focus (DOF) and lithography requirements, and to accurately support further etch steps for construction of multi-level interconnection wires, high-k replacement metal gate transistors, 3D stacked chips, 3D NAND memory cells, etc.

Currently, copper interconnection lines are built using dual damascene processes. During the copper dual damascene process, a seed layer of copper is applied to both wires and vias simultaneously. The ECD process is then used to fill the wires and vias with copper3. After ECD, copper is not only deposited over trenches, but also between them. CMP is used after ECD to remove the excess copper over oxides, and to isolate wires to avoid fatal electrical shorts.

Siemens_Modeling ECD with Machine Learning-2 Electronic computer hardware technology. Motherboard digital chip. Tech science EDA background. Integrated communication processor. Information CPU engineering 3D render background
Figure: Schematic plot of post-ECD surface profile.

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