Model-Based Prediction of Full-Chip SRAF Printability
Sub-resolution Assist Features (SRAFs) are now a viable option for enabling low-k photolithography. Of the many issues arising from SRAF implementation into a production flow, one of the most difficult to resolve can be the prevention of unwanted SRAF printing on the wafer. For simple layouts, the issue can be easily addressed through careful tuning of the photo process and SRAF placement rules. For full-chip product layouts, the difficulty of ensuring that an SRAF will never print becomes far more challenging. In these cases a model-based approach, employed during the technology development cycle, may be more appropriate. The authors have successfully developed such an approach using commercially available ORC (Optical Rule Checking) software. It is based upon a look-up table containing aerial image parameters and SRAF dose printing levels, all of which have been calibrated to on-Silicon data. We will describe in detail the implementation of our approach, and present results on a full 130nm node product layout.
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