Mixed-Signal Verification Challenges
The increasing complexity of today’s Mixed-Signal Integrated Circuits (IC) goes with increasing needs in IC verification to ensure the functionality, but also signal integrity and power consumption. This paper presents the challenges of mixed-signal verification in its two main phases: simulation setting and coverage. It also presents how Freescale took up these challenges during the development of a real-case Sensor IC, using Cadence eManager together with Verilog-AMS, SystemVerilog, and "wreal-based" digital models of the analog environment.
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