Multi-processor synchronization techniques are extensions of well established single processor,multi-threaded, software based synchronization techniques. These multi-processor synchronization techniques require a high level of concurrent visibility of both hardware and processor instruction logic. The risks of effective verification of multi-processor synchronization hardware and processor instruction logic can be best mitigated using a processor driven verification methodology and supporting tools. The stimulus must come from the processor in conjunction with the system level test bench. Debug tools must be non-intrusive and provide concurrent visibility of the hardware and processor state of all processors in a multi-processor design. Although the design challenges of multi-processor synchronization could fill a whole book, take a quick look at the problem to see the acute need for flawless functionality of the hardware and software synchronization logic.

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