Changes in technology and requirements are leading to field programmable gate arrays (FPGAs) playing larger roles in defense electronics designs, and consequently are creating both opportunities and risks. The opportunities include consolidation of systems into smaller and more power-efficient form factors, while the risks include design times, new Department of Defense special requirements, complexity of integration, and changes in required skill sets in the organization.


This white paper looks at the productivity-related risk factors, assesses their impact on designs, and attempts to quantify the risk effects of productivity on the design organization. Once these risks are assessed and defined, an initial cost survey is performed to discover how much of a design effort’s cost is related to the productivity tools used in both system and FPGA development.