Every successive technology node in the silicon manufacturing process timeline presents new and significant technical challenges. Altera works to ensure that the next process node is instituted at the right time to provide the right price point, while designers need to be assured that the added functionality and capability justifies the cost and risk of overcomplicating the design process and silicon delivery schedule. This process has led to the decision to accelerate the development of the 40-nm silicon development node, and make higher density and higher speed transceiver technology available to military users by the beginning of 2009.

This paper discusses the requirements of military designs using FPGAs and the opportunities and risks associated with the transition to the 40-nm technology node. It explains how, by communicating the risks and opportunities of 40-nm FPGAs to its military customers, Altera aims to help digital designers measure the risks and opportunities in defense electronics with these larger and more power-efficient devices.