In these times of short design cycle times, mistakes on the part of designers often give a fatal blow to project schedules, resulting in missed deadlines and/or less than satisfactory quality of the parts. One mistake that is often made is a delivery of a block layout GDSII that’s out of harmony with its previously delivered LEF. Depending on when this mistake is discovered, it could ring the death knells for even the most craftily planned project schedules. The technique presented in this paper empowers the block designer to validate the GDSII against a previously delivered LEF abstract.