Many large systems-on-chip (SoC) designs today incorporate several third-party IP cores that cover a wide range of functionality. These cores often consist of high-performance embedded processors such as those available from ARM. Highly optimized architectures and carefully tuned timing paths are required to achieve ever-increasing performance levels in these processors. Integrating design-for-test capabilities such as memory built-in self-test (BIST) and self-repair capabilities into these cores can affect performance levels because logic typically has to be inserted into functional paths.
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