The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard. This paper details key features and design considerations involved in migrating from a DDR2 interface to a DDR3 system interface, including the Physical Layer (PHY) portion. Areas where backwards compatibility should be preserved are illustrated with an example design, showing how simple changes can provide significant benefits in re-use and system flexibility.