Memory Architectures for High Performance Packet Processing Solutions
Though multi-core processors have been available for many years, only recently has a new class of multi-core processors emerged. These new processors are made up of eight, sixteen, or sixty-four individual processor cores with integrated memory controllers, various I/O interfaces, and separate acceleration engines. Due to their highly integrated nature, they can be used in a variety of system solutions, such as storage, security, wireless base stations, and networking, and are a particularly good fit for moving and processing packets in network applications. As a result, the multi-core processor has begun to replace the very expensive proprietary Application Specific Integrated Circuit (ASIC).
This paper focuses on one critical architectural element of the multi-core processor: the memory subsystem. This component is a primary determinant of the levels of scalability and performance a processor can achieve. The paper compares two memory architectures based on the two leading types of multi-core processors in the market today—the single channel, wide cache line and the dual channel, narrow cache line.
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