Meeting Timing Budgets for DDR Memory Interfaces
Designers commonly use double data rate (DDR) memory IP to boost memory bandwidth, but they often struggle to meet timing budgets for these high-speed interfaces. Designers who incorporate DDR IP into systems-on-chip (SoCs) and use external DRAM have little control over the timing contributions of the SoC or DRAM. Designers do have considerable influence over the impact of the interconnect on timing budgets, however. By using good signal integrity techniques, designers can improve the timing characteristics of the interconnect between the SoC and DRAM.
This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains. It shows how designers can meet timing budgets for double data rate, single data rate, and cross-domain (clock to strobe) timing domains. Finally, it shows how to improve interconnect timing by reducing crosstalk, inter-symbol interference, reflections and skew, and by controlling simultaneously switching output (SSO) effects.
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