With SoCs and embedded systems growing in complexity, being able to accurately predict the performance of a design becomes ever more complex and harder to accomplish. The ability to make an accurate assessment of a system’s performance early in the design process allows designers to make architectural tradeoffs early on, reducing the risk of a redesign.

This paper will discuss a simulation-based virtual prototype methodology that helps designers accurately evaluate the performance of a design before committing to silicon. Through the use of an instrumented hardware prototype, designers will be able to capture and analyze profile data of the design’s processors and system buses. As a result of this visibility, design teams will be able to optimize the performance of the design. This approach not only allows designers the ability to validate whether they have met their performance specifications, but also provides the opportunity to run “what-if analyses,” allowing them to explore alternative design architectures.
Performance hotspots will be examined and alternative solutions to deal with bottlenecks such as hardware/software tradeoffs, software code changes, and alternative bus architectures will also be explored.

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