With the shrinking geometries of advanced process technologies, and the proliferation of systems-on-chip containing multiple millions of transistors, devices that don’t fit the standard mold can produce unintentional effects that can greatly effect the chip as a whole. The only way to be confident that simulations will match the intention of the chip is to use a best-in-class LVS tool that employs a robust ability to measure parameters based on actual physical geometries.

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