This paper provides a review of the Intel 55xx series Nehalem Xeon processor basic memory subsystem architecture, a discussion of design and application tradeoffs that need to be managed when defining the memory subsystem, and an overview of the main memory resources provided on recent AdvancedTCA Nehalem-based single board computers (SBC). It includes discussion of the results of cache and MMU operation, as well as the NUMA (non-uniform memory architecture) used by Intel and others to optimize physical memory resource allocation for simultaneous data accesses on multiple memory channels.