As SoCs become larger and more complex, gate level compilation becomes more resource intensive involving the allocation of multiple resources. The compilation effort becomes more complicated if the testbench is compiled alongside the design. This means every change in the stimuli or testing environment requires re-compilation and a loss of valuable time and resources. A more efficient approach is to compile the design and testbench once and use this model without any further compilation. The fact that multiple compilations are required in the debug phase prevents the use of a single model. Eliminating this need will enhance the efficiency of the Gate Level verification.