Managing Timing Constraints with Precision Synthesis
Managing timing constraints often seems like a painful but necessary evil of field programmable gate array (FPGA) design; but adhering to a constraint methodology is important for implementing a design correctly. With more complex clocking schemes in today’s FPGAs and the prevalence of high-speed I/O interfaces, constraint management is even more critical to system design.
This paper discusses a basic methodology for managing constraints within Precision Synthesis. While Precision Synthesis supports the industry-standard Synopsys Design Constraint (SDC) format, SDC syntax is not the focus of this paper, but rather the method of constraint entry and the identification of missing constraints, particularly within the Precision Synthesis environment.
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