Managing Signal Integrity
Back in the good old days of logic design, we didn’t give much thought to signal integrity. We had 5V power supplies, DIP packages with leads that actually went through the board, and high-speed microprocessors running at a heady 5 MHz.
If you paid a little attention to board layout and put a decent ceramic bypass capacitor next to each chip, you probably didn’t have to worry about your signals. Ones stayed ones and zeroes stayed zeroes. Even 100 mV of noise on a signal wouldn’t be enough to change its logic level.
Today, designers are caught between design requirements for ever-increasing bit rates, faster edge rates, higher clock speeds, and technology advances that keep lowering operating voltages, reducing package sizes and ball pitch, and forcing more components into a smaller amount of board area.
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