Field programmable gate arrays (FPGAs) have become the multi-purpose tools of hardware design. However, as FPGA architectures have evolved to address a wider range of applications, they have also become more complicated to use. Today’s design engineer needs help to efficiently map his design to FPGAs.

Most synthesis tools do a good job of finding the optimal use for the available device resources in mapping a design. This paper explains that while allowing the tool’s heuristics to auto-assign these resources works most of the time, having the capability to easily optimize these assignments can prove invaluable in completing a tough design. This capability is found in Mentor Graphics’ Precision RTL Plus solution, which is also discussed in this paper in detail.

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