As FPGA technology increases gate counts with each new generation, larger scale systems can be implemented using “Platform FPGAs” rather than ASICs. FPGA design starts have grown along with the technology’s capabilities, exceeding those for ASIC by as much as 10 to 1 in 2002. To address the challenges these large FPGA-centric systems present, System-on-Chip (SoC) methodologies developed for ASIC-scale design, such as hardware/software co-verification, must be re-examined. In this article, we will demonstrate the application of the Mentor Graphics Seamless technology on a design targeting the Xilinx Virtex II Pro, with its embedded IBM PowerPC 405 CPU. This design will boot up the Nucleus Plus Real-Time Operating System (RTOS). We will also illustrate performance improvements over conventional HDL simulation when using Seamless.

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