Making the Case for HLS
Algorithms and architectures used in today’s new designs are so complex that traditional design practices are becoming inadequate. This paper gives an overview of the problems associated with the conventional design flow and how they can be addressed with a flow based on the simulation and synthesis of C (ANSI C, C++, or SystemC) representations. By automating an otherwise manual process, HLS eliminates the source of many design errors and accelerates a very long and iterative part of the development cycle.
Note: By clicking on the above link, this paper will be emailed to your EE Times log-in address by Mentor Graphics.
Please disable any pop-up blockers for proper viewing of this Whitepaper.