The forward march of Moore’s Law has resulted in integrated circuit (IC) designs containing more and more functionality on a single chip. While new technology enables expanded capability, such as analog mixed signal systems-on-chip (AMS SoC), it brings with it a new set of design closure problems. These complex designs demand more power and higher clock frequencies; they also create more signal and power net electromigration and substrate noise. If parasitic effects are not accurately handled, a single cell can cause an entire design to fail. This is a huge problem for designers; the failure rate of designs at first silicon is now as high as 80%. Engineers need new, efficient and comprehensive methods of ensuring working designs. Selecting a robust and tightly integrated set of LVS and parasitic extraction tools gives designers the instruments they need to produce accurate and complete data required for mixed level analysis of today’s AMS SoCs.

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