Low Power, High Speed Hybrid DAC Design for Video Application
The aim of this paper is to design a current-mode 16-bits Hybrid digital to analog converter with a high resolution, high speed, and small hardware overhead. This Hybrid DAC design takes advantage of the weighted current-steering approach and the R-βR-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant bit stage while the R-βR ladder approach that is modified form of R-2R approach is used to implement the nine bits in the least significant bit stage. The Hybrid DAC converter was designed with a 0.18µm or 180nm CMOS technology. The simulation results shows that this design achieves a 16 bit resolution with DNL and INL less than 0.58 LSB and 0.42 LSB respectively and operates at 1.8V supply voltage and 97.08MHz operating frequency. The power consumption of the design is 11.3mW, and power dissipation is less than 1.4mW. This design will be used in HDTV application, wireless communication and others communication applications.
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