Low Power Design--where next for Power-Gating?
On-chip power gating is well understood and supported by multi-voltage EDA tools and Unified and Common Power Formats (UPF and CPF), but has limitations. This paper describes new techniques, developed and evaluated in silicon in R&D at ARM, that enhance power gating and address state retention with minimal area and performance impact. Appropriate for Cortex-A class to Cortex-M class SOC designs.
Please disable any pop-up blockers for proper viewing of this Whitepaper.